1. Field of the Invention
This invention relates to a three-dimensional integrated circuit device and its manufacturing method.
2. Description of the Related Arts
Research and study on three-dimensional have been directed heretofore to three-dimensionally intergrated circuits (ICS) stacking two-dimensional ICs, aiming for (1) higher integration and higher density by increasing the number of layers, (2) higher speed of operation of devices by decreasing the wiring length and load capacitance, (3) simultaneous transmission of signals through a number of fine through holes (parallel signal processing) and (4) incorporation of different devices (multi-functions). To realize such three-dimensional integrated circuit devices, SOI (Silicon-on-Insulator) technology and multi-layered wiring technology, among others, have been developed to stack two-dimensional ICs in multiple layers. However, the conventional SOI technology relying on re-crystallization, or the like, could not realize practically acceptable three-dimensional integrated circuit devices because layers stacked by the SOI technology progressively deteriorate in crystallographic property, from the first layer to the second layer, toward upper layers. Additionally, since conventional SOI technology configured to stack layers by one layer over another took a lot of time to complete three-dimensional integrated circuit devices, its cost performance was not good.
There is another technology called CUBIC (Cumulatively Bonded IC) technology has been developed to realize three-dimensional integrated circuit devices. The CUBIC technology is a technique for bonding devices particularly characterized in using a thin IC layer as an elementary unit to be bonded. FIGS. 1 through 6 show a method for fabricating a three-dimensional LSI by the conventional CUBIC technology.
As shown in FIG. 1, in this method, one first makes a two-dimensional LSI 102 on a single-crystal silicon substrate 101 by an LSI process. In the two-dimensional LSI 102, numeral 103 denotes a device isolation oxide film, 104 a MOSFET, 105 a polycrystalline silicon wiring, 106 an inter-layer insulation film, 106a a via hole, 107 a surface metal wiring, 108 an inter-layer insulation film, 108a a via hole, and 109 a tungsten bump. Thereafter, an adhesive 110 is applied onto the surface of the inter-layer insulation film 108, and a support substrate 111 is bonded.
After that, as shown in FIG. 2, the single-crystal silicon substrate 101 is polished and thinned from its bottom surface by selective polishing using the device isolation oxide film 103 as an abrasion stopper to form a single-crystal silicon layer 111.
Next, as shown in FIG. 3, a through hole 112 is made in the device isolation oxide film 103 to reach the poly-crystalline silicon wiring 105, and a bottom metal wiring 113 in contact with the polycrystalline silicon wiring 105 through the through hole 112 is formed on the device isolation oxide film 103. Then, a coating of polyimide 114 is applied on the bottom surface of the two-dimensional LSI 102. After a contact hole 114a is made in the polyimide 114, an Au/In pool 115 is formed in the contact hole 114a.
On the other hand, another two-dimensional LSI 117 as shown in FIG. 4 is made on another single-crystal silicon substrate 116 by an LSI process. In the two-dimensional LSI 117, numeral 118 denotes a device isolation oxide film, 119 a MOSFET, 120 a poly-crystalline silicon wiring, 121 an inter-layer insulation film, 121a a via hole, 122 a surface metal wiring, 123 an inter-layer insulation film, 123a a via hole, and 124 a tungsten bump. Thereafter, a coating of polyimide 125 is applied onto the surface of the inter-layer insulation film 123.
Thereafter, as shown in FIG. 5, the bottom surface of the two-dimensional LSI 102 shown in FIG. 3 is bonded to the top surface of the two-dimensional LSI 117 shown in FIG. 4 with polyimide coatings 114, 125 to conjoin them. At that time, both two-dimensional LSIs 102 and 117 are positionally adjusted to bring the tungsten plug 124 into contact with the Au/In pool 115, then heated to a melting temperature of the Au/In pool 115, around 350.degree. C., for example, and pressed. As a result, the tungsten bump 124 and the Au/In pool 115 are electrically connected.
After that, the support substrate 111 is removed by polishing or etching. As a result, as shown in FIG. 6, the intended three-dimensional LSI including two two-dimensional LSIs 102 and 117 is obtained.
As explained above, since the method for fabricating three-dimensional LSI by CUBIC technology forms two-dimensional LSIs on different poly-crystalline silicon substrates in concurrent, parallel progression, and sequentially conjoins these two-dimensional LSIs under a low temperature (approximately 350.degree. C.), three-dimensional LSIs having a multi-layered structure stacking two or more two-dimensional LSIs can be manufactured efficiently.
However, since the conventional manufacturing method using CUBIC technology relies on selective polishing using the device isolation oxide film 103 as the abrasion stopper to thin the single-crystal silicon substrate 101, the thickness of the single-crystal silicon layer 111 obtained by thinning substantially depends on the thickness of the device isolation oxide film 103. However, the device isolation oxide film 103 is typically 1 .mu.m thick maximum, the CUBIC technology cannot be used to fabricate a two-dimensional LSI requiring at least 1 .mu.m thick single-crystal silicon, such as CCD, MOS-type imaging device, or DRAM using trench-type capacitors as its memory cells. Additionally, the CUBIC technology is expensive in terms of the material cost because it needs single-crystal silicon substrates as many as the number of two-dimensional LSIs to be stacked and support substrates as many as the number of layers minus 1, and results in increasing the manufacturing cost of the three-dimensional LSI.